The present disclosure relates generally to semiconductor device manufacturing, and more particularly to an improved method for dicing a wafer.
Complementary metal oxide semiconductor (CMOS) integrated circuits, including both N-type devices (NMOS) and P-type devices (PMOS), are employed in the large majority of integrated circuits manufactured today. Semiconductor devices in unpackaged form are known as “dies” when certain processing steps are completed on a wafer substrate. The wafer is then diced to have each die detach from the others so that it can be packaged in a desired device unit for further use.
Many wafer materials used for making the dies thereon are of a diamond crystalline structure at a micro level. For example, silicon based wafers are used for manufacturing purposes, as well as other types of wafers such as SiGe or GaAs types. Due to this diamond crystalline structure, the base material of the wafer tends to break easily along a particular natural cleavage direction. As such, the dies processed on a wafer are usually aligned along its natural cleavage direction so that when the wafer is diced the likelihood to crack the wafer in undesired directions is reduced. In other words, as most of the dies are in rectangular shapes, at least one of their four borders are perpendicular to the wafer's natural cleavage direction.
As the technology advances, the semiconductor wafers are getting thinner and thinner, and the likelihood of breaking the wafer while dicing it has been increased. Further, when new technologies allow the dies to be processed on the wafer with its borders at an offset angle from the natural cleavage direction, it is even more likely to crack the wafer when it is undergoing a dicing process.
What is needed is an improved method and system for dicing wafers in a direction that offsets from the natural cleavage direction of the wafer.